Sample: the LilyGO T3-S3 and ESP32 DevKitC, from OGLAST2's satbench

The two boards OGLAST2's satellite bench was built for: the T3-S3 with
the modem on uart0 (GPIO43 and 44), the original ESP32 DevKitC on uart2
(GPIO17 and 16). Both build; neither has run here.

README.md

@@ -155,8 +155,9 @@ real 9704 from Python and from `native_sim`.
 ## Boards
 
 Any board with a free UART. The sample has overlays for `native_sim`,
-NUCLEO-U575ZI-Q, Seeed XIAO ESP32S3 and ESP32-S3-DevKitC, and has run on
+NUCLEO-U575ZI-Q, Seeed XIAO ESP32S3, ESP32-S3-DevKitC, ESP32 DevKitC and
-the first three.
+LilyGO T3-S3 (an out-of-tree board in OGLAST2: build with its
+`-DBOARD_ROOT`). It has run on the first three; all six build.
 
 ## Layout
 

samples/shell/boards/esp32_devkitc_esp32_procpu.overlay

@@ -0,0 +1,12 @@
+/* ESP32 DevKitC (the original ESP32): the modem on uart2, GPIO17 (TX) and
+ * GPIO16 (RX). The console stays on uart0 through the board's USB bridge.
+ * On WROVER modules GPIO16 and GPIO17 belong to the PSRAM: use a WROOM
+ * module, or move uart2's pins here. */
+&uart2 {
+	current-speed = <230400>;
+	status = "okay";
+
+	rockblock {
+		compatible = "rock7,rockblock-9704";
+	};
+};

samples/shell/boards/lilygo_t3s3_esp32s3_procpu.overlay

@@ -0,0 +1,14 @@
+/* LilyGO T3-S3: the modem on uart0, GPIO43 (TX) and GPIO44 (RX) on the
+ * header. The console is on the S3's native USB, so uart0 is free.
+ *
+ * The ESP32-S3's ROM prints on GPIO43 at every reset, before Zephyr runs, so
+ * the modem sees some junk; rbBegin() drains it and resynchronises. If it
+ * ever matters, hold I_EN low until the board is up (iridium-enable-gpios). */
+&uart0 {
+	current-speed = <230400>;
+	status = "okay";
+
+	rockblock {
+		compatible = "rock7,rockblock-9704";
+	};
+};